The present invention relates to masks (or "mask patterns") used in manufacturing a semiconductor device and to a method for manufacturing fine patterns using the same. More particularly, the present invention relates to a mask pattern having additional patterns on the spaces thereof so as to reduce the exposing dosage and a manufacturing method of fine patterns having an improved profile, which ultimately increases the cell capacitance of a semiconductor device significantly.
As semiconductor devices having high-integration and high-performance have been developed, more complicated structures have been employed, and as the result, techniques for manufacturing fine patterns on a semiconductor substrate are increasingly needed. It is widely known that such patterns of the semiconductor devices are manufactured through photolithography.
Photolithography is an essential process in manufacturing semiconductor devices. For example, in order to limit the selective diffusion region, photoresist material is coated on a dielectric layer of semiconductor substrate and is exposed and developed to form a photoresist pattern. Using the patterned photoresist layer, the dielectric layer is etched to form a window, and the patterned dielectric layer is used as a mask for selective diffusion process.
Recently, with the development of semiconductor manufacturing techniques (especially photolithography) and the reduction of design rules to submicron levels, the high-integration of semiconductor devices has been accelerated. However, certain factors greatly restrict the effective area of the capacitor and impedes further development of the semiconductor devices. Despite such restrictions, sufficient cell capacitance should be secured in order to improve the read-out capability of a semiconductor memory cell and to reduce the soft error rate. Therefore, research and development has continued in the field of photolithography, so as to find solutions to these problems.
In photolithography, a mask pattern is essential for the formation of any pattern on a substrate. FIG. 1 is an example of a mask pattern layout for manufacturing a cell capacitor.
Referring to FIG. 1, a mask pattern P1 is for forming an active region, i.e., source and drain regions, a mask pattern P2 is for forming a gate electrode, a mask pattern P3 is for forming the wiring which connects the source region and a storage node, a mask pattern P4 is for forming a bit line and has a central contact hole designating the point of symmetry, and a mask pattern P5 is for forming the storage nodes. This layout is for forming a cell capacitor along a bit line and the manufacturing process therefor can be described as follows.
First, the bit line is formed to contact the drain region of a transistor, and dielectric material is deposited on the whole surface of the substrate to electrically insulate the bit line. Then, the dielectric material is partially removed to expose the portion which is connected electrically with the transistor's source region, and a storage node is formed on the insulation material to interconnect with the source region of the transistor through the partially removed portion of the insulation material.
To form resist patterns for the storage node, the above photolithography process is employed using the mask pattern illustrated in FIG. 2. However, the edges become rounded off in the actually manufactured resist pattern on the substrate, due to the loss of resist at the edges thereof. This problem, often explained as a proximity effect, is serious when manufacturing rectangular pattern and can be exemplified as follows. During exposure, those portions marked with an "a" in FIG. 2 are relatively over-exposed, so that the patterns themselves are actually developed such that the size of the desired pattern (which would ideally correspond to the size of the mask portions indicated by numeral 10) is reduced, thereby producing a smaller storage node.
Accordingly, research and development on improving the structure of a storage node constituting a cell capacitor has continued. For example, the fin-structure type (of Fujitsu), the box type (of Toshiba), the spread-stacked capacitor structure (also by Toshiba), the cylinder structure (Mitsubishi) and others are suggested.
However, such efforts to increase cell capacity by improving the structure of the storage node are not easy, in light of design rule restrictions and an increase in the defect ratio owing to a more complicated process. Thus, the need for such a method to overcome this problem becomes heightened to ensure sufficient cell capacity.
Meanwhile, a method for manufacturing patterns using the photolithography will be described in detail below.
First, on a substrate desired to be patterned such as a semiconductor wafer, a dielectric layer or a conductive layer, a photoresist layer made of organic materials which has the characteristic of changing its solubility to an alkaline solution before and after exposure to ultraviolet light, X-ray radiation, etc. is formed. The resist layer is selectively exposed by employing a mask pattern over the photoresist layer, and is then developed to remove the portion having high solubility (in the case of a positive resist, removing the exposed portion) and to thereby leave the portion having low solubility and form resist patterns. Etching the substrate of the portion on which the resist has been removed to form patterns, and then removing the remaining resist, gives desired patterns.
Since fine patterns of high resolution can be obtained, the patterning method by the above-described photolithography is widely used. However, in order to form finer patterns, still further improvement in the manufacturing process is necessary.
The linewidth of the fine patterns formed after developing the photoresist layer is required to be the same as that of the photomask at a particular reduction ratio. However, since many process steps are required in photolithography, it is very difficult to keep the linewidth of the patterns consistent. The variation of the linewidth is mainly due to (a) the difference of exposing dosage owing to the difference of the thickness of resist, and (b) light interference due to the diffused reflection of the light over the topography (S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, vol. 1, p 439, 1986, herein incorporated by reference). A more detailed description is given below.
Photoresist is coated on a substrate while spinning the substrate at a speed of 100 to 1000 rpm. Then, the rotation speed of the substrate is increased to about 2000 to 6000 rpm and the photoresist is radially spread by the centrifugal force, to form a photoresist layer having uniform thickness on the substrate.
At this time, if the substrate has already been patterned, a bulk effect (a phenomena of the photoresist being partially thickened owing to a step) is generated where the step exists.
Referring to FIGS. 3A and 3B, an example of the conventional line & space-type mask pattern (1) in FIG. 3A is used to expose a predetermined portion of a resist layer (2) formed on a substrate (3) having a step (S) (FIG. 3B). Here, the resist layer (2) formed on the substrate (3) with step has a thickness difference according to the height differential of the step. When exposing the resist layer using the conventional line & space-type mask pattern on the portion having a step, that is, having different resist thicknesses, since the same dosage is applied throughout the whole resist layer regardless of thickness, various problems occur. In particular, as devices become highly integrated, complicated structures are employed, and as the result, the number of steps increases. Thus, when coating the photoresist, the resist patterns having thickness differences at the steps are formed, and with the increased number of steps, patterns having a uniform profile may not result and pattern bridging and residue are increasingly induced. In FIG. 3B, given the use of a positive photoresist, if the exposing dosage is adjusted to accommodate the thinner portion of the photoresist (A), the lower portion of the step (B), i.e., the thicker portion of the photoresist, is under-exposed and, after development, this thicker portion may not be entirely developed, so that a residue remains. On the other hand, if the exposing dosage is set for the thicker portion of the photoresist, the upper portion of the step, i.e., the thinner portion of the photoresist, is over-exposed, and results in thinner patterns than expected.
Such an undesirable phenomenon is the result of the following circumstances. To form an excellent resist pattern, the focus of the light when performing the light exposure should coincide with a central line C of a thickness of the resist layer. That is, since the exposing area at the surface of the resist is symmetrical to the light exposing area at the lower surface of the resist with respect to the focal point, when the focal point coincides central line C of the thickness of the resist layer, the light exposing areas of the top and bottom surfaces thereof are identical, thereby enabling a sharply defined light intensity. However, since the thickness of the resist layer formed on the wafer having a step is not constant according to the substrate area, it is virtually impossible to make the central line C of the thickness of the whole resist layer coincide with the focal point of the light. That is, for example, since the focal line of the light at the step having a relatively thick resist is above the central line with respect thereto, the lower exposing range of the resist becomes broader than the upper exposing range. This means that the exposure energy dosage at the lower portion of the resist is relatively insufficient. The insufficient exposure generates undesirable variations in linewidth, bridging, residue, etc. Accordingly, the resist pattern profile becomes poor, so that the substrate cannot be etched properly.
As described above, when a mask pattern consistent with a desired resist pattern is used to form resist patterns, a dosage difference is induced according to the pattern shape, and thus, patterns having good and uniform profile may not be obtained.